Datasheet

Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 554 of 788
REJ09B0300-0300
R/W
Bit Bit Name Initial Value Slave Host Description
4 SMIE3B 0 R/W — Host SMI Interrupt Enable 3B
Enables or disables a host SMI interrupt request
when OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and
SMIE3B is disabled
[Clearing conditions]
• Writing 0 to SMIE3B
• LPC hardware reset, LPC software reset
• Clearing OBF3B to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF3B to 1
is enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3B = 0
3 SMIE3A 0 R/W — Host SMI Interrupt Enable 3A
Enables or disables a host SMI interrupt request
when OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and
SMIE3A is disabled
[Clearing conditions]
• Writing 0 to SMIE3A
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3A = 0