Datasheet

Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 551 of 788
REJ09B0300-0300
R/W
Bit Bit Name Initial Value Slave Host Description
0OBF3A0 R/(W)
*
R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host
processor reads ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.
• STR3 (TWRE = 0 and SELSTR3 = 1)
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU37
DBU36
DBU35
DBU34
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3C/D3 0 R R Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0 R/W R Defined by User
The user can use this bit as necessary.