Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 514 of 788
REJ09B0300-0300
18.3.2 Host Interface Control Register (HICR)
Host Interface Control Register 2 (HICR2)
HICR controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2
controls host interface channel 3 and 4 interrupts.
• HICR
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 to 3  All 1  Reserved
These bits are always read as 1 and cannot be
modified.
2IBFIE20 R/W Input Data Register Full Interrupt Enable 2
Enables or disables the IBF2 interrupt to the
internal CPU.
0: Input data register (IDR_2) reception
completed interrupt request disabled
1: Input data register (IDR_2) reception
completed interrupt request enabled
1IBFIE10 R/W Input Data Register Full Interrupt Enable 1
Enables or disables the IBF1 interrupt to the
internal CPU.
0: Input data register (IDR_1) reception
completed interrupt request disabled
1: Input data register (IDR_1) reception
completed interrupt request enabled