Datasheet

Section 1 Overview
Rev. 3.00 Mar 21, 2006 page 1 of 788
REJ09B0300-0300
Section 1 Overview
1.1 Features
• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
Data transfer controller (DTC)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Timer connection
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI, IrDA)
I
2
C bus interface (IIC)
Keyboard buffer controller
Host interface X-BUS interface (XBS)
Host interface LPC interface (LPC)
*
8-bit D/A converter
10-bit A/D converter
Clock pulse generator
Note: * The LPC function is not supported by H8S/2148B and H8S/2145B (5-V version).