Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 509 of 788
REJ09B0300-0300
Section 18 Host Interface X-Bus Interface (XBS)
This LSI has an on-chip host interface (HIF) that enables connection to the ISA bus (X-BUS) and
has an on-chip LPC interface. In the following text, these two host interfaces (HIFs) are referred to
as XBS and LPC, respectively.
The XBS provides a four-channel parallel interface between the chip’s internal CPU and a host
processor.
Communication is carried out via seven control signals from the host processor (CS1, CS2 or
ECS2, CS3, CS4, HA0, IOR, and IOW), six output signals to the host processor (GA20, HIRQ1,
HIRQ11, HIRQ12, HIRQ3, and HIRQ4), and an 8-bit bidirectional command/data bus (HDB7 to
HDB0). The CS1, CS2 (or ECS2), CS3 and CS4 signals select one of the four interface channels.
18.1 Features
• Control of the fast GATE A20 function
• Shutdown of the XBS module by the HIFSD pin
• Five host interrupt requests
IFHSTX0A_000020020700