Datasheet

Section 17 Keyboard Buffer Controller
Rev. 3.00 Mar 21, 2006 page 506 of 788
REJ09B0300-0300
17.4.7 Receive Timing
Figure 17.12 shows the receive timing.
N + 1 N + 2N
KCLK (pin)
Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active
mode.
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
Internal KD
(KDI)
KBBR7 to
KBBR0
φ
*
Figure 17.12 Receive Counter and KBBR Data Load Timing