Datasheet

Section 17 Keyboard Buffer Controller
Rev. 3.00 Mar 21, 2006 page 503 of 788
REJ09B0300-0300
17.4.4 KCLKI and KDI Read Timing
Figure 17.9 shows the KCLKI and KDI read timing.
T1 T2
φ
*
Internal read
signal
KCLK, KD
(pin state)
KCLKI, KDI
(register)
Internal data bus
(read data)
Note:
*
The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.9 KCLKI and KDI Read Timing