Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 468 of 788
REJ09B0300-0300
16.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 16.26 to 16.28 show the IRIC set timing and SCL control.
SCL
SDA
IRIC
User processing
Clear IRIC
231A87
321987
When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
SCL
SDA
IRIC
User processing
Clear IRIC Clear IRICWrite to ICDR (transmit)
or read from ICDR (receive)
1A87
1987
Figure 16.26 IRIC Setting Timing and SCL Control (1)