Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 436 of 788
REJ09B0300-0300
16.3.7 DDC Switch Register (DDCSWR)
DDCSWR controls the IIC_0 automatic format switching function and IIC internal latch
clearance.
Bit Bit Name Initial Value R/W Description
7 SWE 0 R/W DDC Mode Switch Enable
0: Disables automatic switching of IIC channel 0 from
formatless mode to I
2
C bus format
1: Enables automatic switching of IIC channel 0 from
formatless mode to I
2
C bus format
6 SW 0 R/W DDC Mode Switch
0: Uses IIC channel 0 with the I
2
C bus format
1: Uses IIC channel 0 in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when
SWE = 1
5 IE 0 R/W DDC Mode Switch Interrupt Enable Bit
0: Disables interrupts when automatic format switching is
executed
1: Enables interrupts when automatic format switching is
executed
4IF 0 R/(W)
*
1
DDC Mode Switch Interrupt Flag
Indicates an interrupt request to the CPU is generated
when automatic format switching is executed for IIC_0.
[Setting condition]
When a falling edge is detected on the SCL pin when
SWE = 1
[Clearing condition]
When 0 is written in IF after reading IF = 1