Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 432 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
5 IRTR 0 R/(W)
*
I
2
C Bus Interface Continuous Transfer Interrupt Request
Flag
Indicates that the I
2
C bus interface has issued an interrupt
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is possible.
When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
[Setting conditions]
I
2
C bus format slave mode:
• When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format mode
with I
2
C bus format, or formatless mode:
• When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
• When 0 is written after reading IRTR = 1
• When the IRIC flag is cleared to 0 while ICE is 1
4 AASX 0 R/(W)
*
Second Slave Address Recognition Flag
In I
2
C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition matches bits
SVAX6 to SVAX0 in SARX.
[Setting condition]
When the second slave address is detected in slave
receive mode and FSX = 0 in SARX
[Clearing conditions]
• When 0 is written in AASX after reading AASX = 1
• When a start condition is detected
• In master mode