Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 415 of 788
REJ09B0300-0300
Figure 16.1 shows a block diagram of the I
2
C bus interface. Figure 16.2 shows an example of I/O
pin connections to external circuits. Since I
2
C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 28, Electrical Characteristics.
φ
SCL
PS
Noise
canceler
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
ICCR
Clock
control
ICXR
ICMR
ICSR
ICDRS
Address
comparator
SAR, SARX
SDA
Noise
canceler
Interrupt
generator
Interrupt
request
Internal data bus
ICDRR
ICDRT
Formatless dedicated
clock (IIC_0 only)
Legend:
ICCR:
ICMR:
ICSR:
ICDR:
ICXR:
SAR:
SARX:
PS:
I
2
C bus control register
I
2
C bus mode register
I
2
C bus status register
I
2
C bus data register
I
2
C bus extended control register
Slave address register
Slave address register X
Prescaler
Figure 16.1 Block Diagram of I
2
C Bus Interface