Datasheet

Rev. 3.00 Mar 21, 2006 page xlv of liv
Figure 19.5 Power-Down State Termination Timing.............................................................. 571
Figure 19.6 SERIRQ Timing................................................................................................... 572
Figure 19.7 Clock Start Request Timing................................................................................. 574
Figure 19.8 HIRQ Flowchart (Example of Channel 1) ........................................................... 577
Section 20 D/A Converter
Figure 20.1 Block Diagram of D/A Converter........................................................................ 579
Figure 20.2 D/A Converter Operation Example...................................................................... 583
Section 21 A/D Converter
Figure 21.1 Block Diagram of A/D Converter........................................................................ 586
Figure 21.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected)............................................................................................................... 593
Figure 21.3 A/D Conversion Timing ...................................................................................... 594
Figure 21.4 External Trigger Input Timing............................................................................. 595
Figure 21.5 A/D Conversion Accuracy Definitions................................................................ 597
Figure 21.6 A/D Conversion Accuracy Definitions................................................................ 597
Figure 21.7 Example of Analog Input Circuit......................................................................... 598
Figure 21.8 Example of Analog Input Protection Circuit ....................................................... 600
Figure 21.9 Equivalent Circuit of Analog Input Pin ............................................................... 600
Section 23 ROM
Figure 23.1 Block Diagram of Flash Memory ........................................................................ 604
Figure 23.2 Flash Memory State Transitions .......................................................................... 605
Figure 23.3 Boot Mode ........................................................................................................... 606
Figure 23.4 User Program Mode (Example)........................................................................... 607
Figure 23.5 64-Kbyte Flash Memory Block Configuration .................................................... 608
Figure 23.6 128-Kbyte Flash Memory Block Configuration .................................................. 609
Figure 23.7 256-Kbyte Flash Memory Block Configuration .................................................. 610
Figure 23.8 On-Chip RAM Area in Boot Mode...................................................................... 621
Figure 23.9 ID Code Area....................................................................................................... 622
Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode..................... 623
Figure 23.11 Program/Program-Verify Flowchart.................................................................... 625
Figure 23.12 Erase/Erase-Verify Flowchart.............................................................................. 627
Figure 23.13 Memory Map in Programmer Mode .................................................................... 630
Section 24 Clock Pulse Generator
Figure 24.1 Block Diagram of Clock Pulse Generator............................................................ 633
Figure 24.2 Typical Connection to Crystal Resonator ............................................................ 634
Figure 24.3 Equivalent Circuit of Crystal Resonator .............................................................. 634
Figure 24.4 Example of External Clock Input......................................................................... 635