Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 413 of 788
REJ09B0300-0300
Section 16 I
2
C Bus Interface (IIC) (Optional)
The I
2
C bus interface is provided as an optional function. Note the following point when using this
optional function.
• Although the product type name is identical, please contact Renesas before using this optional
function on an F-ZTAT version product.
This LSI has a two-channel I
2
C bus interface. The I
2
C bus interface conforms to and provides a
subset of the Philips I
2
C bus (inter-IC bus) interface functions. The register configuration that
controls the I
2
C bus differs partly from the Philips configuration, however.
16.1 Features
• Selection of addressing format or non-addressing format
 I
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
 Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
 Formatless (for IIC_0 only): non-addressing format with a clock pin dedicated for
formatless; for slave operation only
• Conforms to Philips I
2
C bus interface (I
2
C bus format)
• Two ways of setting slave address (I
2
C bus format)
• Start and stop conditions generated automatically in master mode (I
2
C bus format)
• Selection of the acknowledge output level in reception (I
2
C bus format)
• Automatic loading of an acknowledge bit in transmission (I
2
C bus format)
• Wait function in master mode (I
2
C bus format)
 A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
 The wait can be cleared by clearing the interrupt flag.
• Wait function (I
2
C bus format)
 A wait request can be generated by driving the SCL pin low after data transfer.
 The wait request is cleared when the next transfer becomes possible.
• Interrupt sources
 Data transfer end (including when a transition to transmit mode with I
2
C bus format occurs,
when ICDR data is transferred, or during a wait state)
IFIIC60A_000020020700