Datasheet

Rev. 3.00 Mar 21, 2006 page xli of liv
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used) ............................................. 282
Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Used) .................................................... 283
Section 12 8-Bit Timer (TMR)
Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)....................................... 288
Figure 12.2 Block Diagram of 8-Bit Timers (TMR_Y and TMR_X)..................................... 289
Figure 12.3 Pulse Output Example.......................................................................................... 301
Figure 12.4 Count Timing for Internal Clock Input................................................................ 302
Figure 12.5 Count Timing for External Clock Input (Both Edges)......................................... 302
Figure 12.6 Timing of CMF Setting at Compare-Match......................................................... 303
Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal ......................... 303
Figure 12.8 Timing of Counter Clear by Compare-Match...................................................... 304
Figure 12.9 Timing of Counter Clear by External Reset Input ............................................... 304
Figure 12.10 Timing of OVF Flag Setting................................................................................ 305
Figure 12.11 Timing of Input Capture Operation ..................................................................... 307
Figure 12.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR
and TICRF Read)................................................................................................. 307
Figure 12.13 Input Capture Signal Selection ............................................................................ 308
Figure 12.14 Conflict between TCNT Write and Clear ............................................................ 310
Figure 12.15 Conflict between TCNT Write and Increment..................................................... 311
Figure 12.16 Conflict between TCOR Write and Compare-Match........................................... 312
Section 13 Timer Connection
Figure 13.1 Block Diagram of Timer Connection................................................................... 318
Figure 13.2 Timing Chart for PWM Decoding ....................................................................... 330
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............ 331
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)............................ 331
Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided
Waveform Periods ............................................................................................... 334
Figure 13.6 2fH Modification Timing Chart........................................................................... 335
Figure 13.7 Fall Modification and IHI Synchronization Timing Chart................................... 337
Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart.............................................. 340
Figure 13.9 CBLANK Output Waveform Generation ............................................................ 343
Section 14 Watchdog Timer (WDT)
Figure 14.1 Block Diagram of WDT....................................................................................... 346
Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation ............................................. 353
Figure 14.3 Interval Timer Mode Operation........................................................................... 354
Figure 14.4 OVF Flag Set Timing........................................................................................... 354