Datasheet

Section 15 Serial Communication Interface (SCI and IrDA)
Rev. 3.00 Mar 21, 2006 page 369 of 788
REJ09B0300-0300
15.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode Bit Rate Error
Asynchronous mode
B =
64 × 2 × (N+1)
2n-1
φ × 10
6
Error (%) = {
B × 64 × 2 × (N+1)
2n-1
φ × 10
6
– 1 } × 100
Clocked synchronous mode
B =
64 × 2 × (N+1)
2n-1
φ × 10
6
—
Legend:
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1 CKS0 n
000
011
102
113
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock
input.