Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 3.00 Mar 21, 2006 page 349 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to. The overflow
frequency for φ = 10 MHz is enclosed in parentheses.
000: φ/2 (frequency: 51.2 µs)
001: φ/64 (frequency: 1.64 ms)
010: φ/128 (frequency: 3.28 ms)
011: φ/512 (frequency: 13.1 ms)
100: φ/2048 (frequency: 52.4 ms)
101: φ/8192 (frequency: 209.7 ms)
110: φ/32768 (frequency: 0.84 s)
111: φ/131072 (frequency: 3.36 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.