Datasheet

Rev. 3.00 Mar 21, 2006 page xxxviii of liv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B,
and H8S/2148B.................................................................................................... 3
Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B..................................... 4
Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B..... 5
Figure 1.4 Pin Arrangement of H8S/2160B and H8S/2161B................................................ 6
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. 29
Figure 2.2 Stack Structure in Normal Mode ......................................................................... 29
Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... 30
Figure 2.4 Stack Structure in Advanced Mode ..................................................................... 31
Figure 2.5 Memory Map ....................................................................................................... 32
Figure 2.6 CPU Internal Registers......................................................................................... 33
Figure 2.7 Usage of General Registers.................................................................................. 34
Figure 2.8 Stack .................................................................................................................... 35
Figure 2.9 General Register Data Formats (1) ...................................................................... 37
Figure 2.9 General Register Data Formats (2) ...................................................................... 38
Figure 2.10 Memory Data Formats......................................................................................... 39
Figure 2.11 Instruction Formats (Examples)........................................................................... 51
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ................ 54
Figure 2.13 State Transitions................................................................................................... 58
Section 3 MCU Operating Modes
Figure 3.1 Address Map for H8S/2140B and H8S/2160B (1)............................................... 71
Figure 3.2 Address Map for H8S/2140B and H8S/2160B (2)............................................... 72
Figure 3.3 Address Map for H8S/2141B and H8S/2161B (1)............................................... 73
Figure 3.4 Address Map for H8S/2141B and H8S/2161B (2)............................................... 74
Figure 3.5 Address Map for H8S/2145BV (1)...................................................................... 75
Figure 3.6 Address Map for H8S/2145BV (2)...................................................................... 76
Figure 3.7 Address Map for H8S/2145B (1)......................................................................... 77
Figure 3.8 Address Map for H8S/2145B (2)......................................................................... 78
Figure 3.9 Address Map for H8S/2148B (1)......................................................................... 79
Figure 3.10 Address Map for H8S/2148B (2)......................................................................... 80
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 3) .................................................................................... 84
Figure 4.2 Stack Status after Exception Handling................................................................. 86