Datasheet

Section 13 Timer Connection
Rev. 3.00 Mar 21, 2006 page 333 of 788
REJ09B0300-0300
Table 13.6 Examples of TCR and TCSR Settings
Register Bit Abbreviation Contents Description
7CMIEB 0
6CMIEA 0
5OVIE 0
Interrupts due to compare-match and
overflow are disabled
4 and 3 CCLR1 and
CCLR0
11 TCNT is cleared by the rising edge of
the external reset signal (inverse of
the IVI signal)
TCR in TMR_1
2 to 0 CKS2 to CKS0 101 TCNT is incremented on the rising
edge of the external clock (IHI signal)
0011 Not changed by compare-match B;
output inverted by compare-match A
(toggle output): Division by 512
TCSR in TMR_1 3 to 0 OS3 to OS0
1001 When TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: Division by
256
6 IEDGB 0/1 0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
TCR in FRT
1 and 0 CKS1 and CKS0 01 FRC is incremented on internal
clock: φ/8
TCSR in FRT 0 CCLRA 0 FRC clearing is disabled