Datasheet

Section 13 Timer Connection
Rev. 3.00 Mar 21, 2006 page 322 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
3
2
1
0
HFINV
VFINV
HIINV
VIINV
0
0
0
0
R/W
R/W
R/W
R/W
Input Synchronization Signal Inversion
These bits select inversion of the input phase of the
spare horizontal synchronization signal (HFBACKI),
the spare vertical synchronization signal (VFBACKI),
the horizontal synchronization signal (HSYNCI),
composite synchronization signal (CSYNCI), and the
vertical synchronization signal (VSYNCI).
• HFINV
0: The HFBACKI pin state is used directly as the
HFBACKI input
1: The HFBACKI pin state is inverted before use as
the HFBACKI input
• VFINV
0: The VFBACKI pin state is used directly as the
VFBACKI input
1: The VFBACKI pin state is inverted before use as
the VFBACKI input
• HIINV
0: The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1: The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
• VIINV
0: The VSYNCI pin state is used directly as the
VSYNCI input
1: The VSYNCI pin state is inverted before use as the
VSYNCI input
Legend:
X: Don’t care
Table 13.2 Synchronization Signal Connection Enable
Bit 5 Description
SCONE Mode FTIA FTIB FTIC FTID TMCI1 TMRI1
0 Normal connection (Initial value) FTIA
input
FTIB
input
FTIC
input
FTID
input
TMCI1
input
TMRI1
input
1 Synchronization signal
connection mode
IVI
signal
TMO1
signal
VFBACKI
input
IHI
signal
IHI
signal
IVI inverse
signal