Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 298 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMOY pin
*
2
output level is to
be changed by compare-match B of TCORB_Y and
TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMOY pin
*
2
output level is to
be changed by compare-match A of TCORA_Y and
TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Notes: 1. Only 0 can be written, for flag clearing.
2. This product does not have a TMOY external output pin.
• TCSR_X
Bit Bit Name Initial Value R/W Description
7CMFB0 R/(W)
*
Compare-Match Flag B
[Setting condition]
When the values of TCNT_X and TCORB_X match
[Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
6CMFA0 R/(W)
*
Compare-Match Flag A
[Setting condition]
When the values of TCNT_X and TCORA_X match
[Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt