Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 293 of 788
REJ09B0300-0300
Table 12.2 Clock Input to TCNT and Count Condition
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Disables clock input
0 0 1 — 0 Increments at falling edge of internal clock φ/8
0 0 1 — 1 Increments at falling edge of internal clock φ/2
0 1 0 — 0 Increments at falling edge of internal clock φ/64
0 1 0 — 1 Increments at falling edge of internal clock φ/32
0 1 1 — 0 Increments at falling edge of internal clock φ/1024
0 1 1 — 1 Increments at falling edge of internal clock φ/256
TMR_0
1 0 0 — — Increments at overflow signal from TCNT_1
*
TMR_1 0 0 0 — — Disables clock input
0 0 1 0 — Increments at falling edge of internal clock φ/8
0 0 1 1 — Increments at falling edge of internal clock φ/2
0 1 0 0 — Increments at falling edge of internal clock φ/64
0 1 0 1 — Increments at falling edge of internal clock φ/128
0 1 1 0 — Increments at falling edge of internal clock φ/1024
0 1 1 1 — Increments at falling edge of internal clock φ/2048
1 0 0 — — Increments at compare-match A from TCNT_0
*
0 0 0 — — Disables clock input
0 0 1 — — Increments at falling edge of internal clock φ/4
0 1 0 — — Increments at falling edge of internal clock φ/256
0 1 1 — — Increments at falling edge of internal clock φ/2048
TMR_Y
1 0 0 — — Disables clock input
0 0 0 — — Disables clock input
0 0 1 — — Increments at falling edge of internal clock φ
0 1 0 — — Increments at falling edge of internal clock φ/2
0 1 1 — — Increments at falling edge of internal clock φ/4
TMR_X
1 0 0 — — Disables clock input
1 0 1 — — Increments at rising edge of external clock
1 1 0 — — Increments at falling edge of external clock
Common
1 1 1 — — Increments at both rising and falling edges of
external clock.
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as
the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated.