Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 273 of 788
REJ09B0300-0300
11.5.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
11.5 shows the timing of this operation for compare-match A.
φ
FRC
OCRA
NNN + 1 N + 1
NN
Compare-match
A signal
OLVLA
Output compare A
output pin FTOA
Clear
*
Note: * Indicates instruction execution by software.
Figure 11.5 Timing of Output Compare A Output
11.5.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
FRC N H'0000
Compare-match
A signal
Figure 11.6 Clearing of FRC by Compare-Match A Signal