Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 202 of 788
REJ09B0300-0300
• P96/φ/EXCL
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P96DDR bit.
P96DDR 0 1
EXCLE 0 1 0
Pin Function P96 input pin EXCL input pin φ output pin
Note: When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
• P95/AS/IOS/CS1
The pin function is switched as shown below according to the combination of operating mode,
the IOSE bit in SYSCR, the HI12E bit in SYSCR2, and the P95DDR bit.
Operating
Mode
Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0)
HI12E — 0 1
P95DDR — 0 1 —
IOSE 0 1 ———
Pin Function AS
output pin
IOS
output pin
P95
input pin
P95
output pin
CS1
input pin
• P94/HWR/IOW
The pin function is switched as shown below according to the combination of operating mode,
the HI12E bit in SYSCR2, and the P94DDR bit.
Operating
Mode
Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0)
HI12E — 0 1
P94DDR — 0 1 —
Pin Function HWR
output pin
P94
input pin
P94
output pin
IOW
input pin