Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Mar 21, 2006 page 151 of 788
REJ09B0300-0300
7.2.8 DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
DTVECR is initialized to H'00 at a reset and in hardware standby mode.
Bit Bit Name Initial Value R/W Description
7 SWDTE 0 R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can always be
written to this bit. 0 can be written to after reading 1
from this bit.
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of
transfers have not ended.
• When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
[Holding conditions]
• When the DISEL bit is 1 and data transfer has
ended
• When the specified number of transfers have ended.
• During data transfer activated by software
6
5
4
3
2
1
0
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to DTVEC0 =
H'10, the vector address is H'0420. When the SWDTE
bit is 0, these bits can be written to.