Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 133 of 788
REJ09B0300-0300
16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be
inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Undefined
Write
High level
AS/IOS (IOSE = 1)
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)