Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 130 of 788
REJ09B0300-0300
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
6.5.2 Valid Strobes
Table 6.4 shows the data buses used and valid strobes for each access space.
In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the
HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.4 Data Buses Used and Valid Strobes
Area
Access
Size
Read/
Write Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
Lower Data
Bus (D7 to D0)
Read — RD Ports or others
8-bit access
space
Byte
Write — HWR
Valid
Ports or others
Even Valid InvalidRead
Odd
RD
Invalid Valid
Even HWR Valid Undefined
Byte
Write
Odd LWR Undefined Valid
Read — RD Valid Valid
16-bit access
space
Word
Write — HWR, LWR Valid Valid
Note: Undefined: Undefined data is output.
Invalid: Input state with the input value ignored.
Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used
as the data bus.