Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 127 of 788
REJ09B0300-0300
Table 6.2 shows the bus specifications for the basic bus interface of each area.
Table 6.2 Bus Specifications for Basic Bus Interface
Bus Specifications
ABW AST WMS1 WMS0 WC1 WC0 Bus Width
Number of
Access
States
Number of
Program
Wait States
0 ————16 2 0
01—— 3 0
000
11
02
0
1
—* —*
1
1
16
3
3
0 ————8 2 0
01—— 3 0
000
11
02
1
1
—* —*
1
1
8
3
3
Note: * Other than WMS1 = 0 and WMS0 = 1
6.4.2 Advanced Mode
The external address space is initialized as the basic bus interface and a 3-state access space. In
on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM,
internal I/O registers, and their reserved areas is specified as the external address space. The on-
chip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1. The on-
chip RAM and its reserved area are disabled and corresponding addresses are the external address
space when the RAME bit is cleared to 0.
6.4.3 Normal Mode
The external address space is initialized as the basic bus interface and a 3-state access space. In
on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O
registers is specified as the external address space. In on-chip ROM enable extended mode, the
address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved
areas is specified as the external address space. The on-chip RAM area is enabled when the