Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 124 of 788
REJ09B0300-0300
6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space or the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit Bit Name Initial Value R/W Description
7— 1 R/WReserved
This bit should not be written by 0.
6 ICIS0 1 R/W Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle
cycle between bus cycles when the external write
cycle follows the external read cycle.
0: Idle cycle not inserted when the external write cycle
follows the external read cycle
1: 1-state idle cycle inserted when the external write
cycle follows the external read cycle
5 BRSTRM 0 R/W Burst ROM Enable
Selects the bus interface for the external address
space.
0: Basic bus interface
1: Burst ROM interface
4 BRSTS1 1 R/W Burst Cycle Select 1
Selects the number of states in the burst cycle of the
burst ROM interface.
0: 1 state
1: 2 states
3 BRSTS0 0 R/W Burst Cycle Select 0
Selects the number of words that can be accessed by
burst access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
2  0R/WReserved
This bit should not be written by 0.
1
0
IOS1
IOS0
1
1
R/W
R/W
IOS Select 1, 0
Select the address range where the IOS signal is
output. For details, refer to table 6.3.