Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 21, 2006 page 114 of 788
REJ09B0300-0300
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See table 7.1 for the respective
priority.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.7 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTCE bit of DTC's DTCER, and the DISEL bit of DTC's MRB.
Table 5.7 Interrupt Source Selection and Clearing Control
Settings
DTC Interrupt Sources Selection/Clearing Control
DTCE DISEL DTC CPU
0 * ×
O
0
O
×1
1
oO
Legend:
O
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
o
: The relevant interrupt is used. The interrupt source is not cleared.
×: The relevant interrupt cannot be used.
*:Don’t care
Note: The SCI, IIC, LPC, or A/D converter interrupt source is cleared when the DTC reads or
writes to the prescribed register, and is not dependent upon the DISEL bit.