Datasheet

Rev. 3.00 Mar 21, 2006 page xiv of liv
Item Page Revision (See Manual for Details)
16.4.4 Master
Receive Operation
Figure 16.15 Sample
Flowchart for
Operations in Master
Receive (Receiving a
Single Byte) (WAIT =
1)
453 Figure 16.15 amended
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC flag in ICCR
IRIC = 1?
Yes
No
[2] Start receiving. The first read
is a dummy read.
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock)
[7] Set acknowledge data for
the last reception.
Figure 16.16 Example
of Master Receive
Mode Operation
Timing (MLS = ACKB
= 0, WAIT = 1)
456 Figure 16.16 amended
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
SCL
(master output)
Bit 5 Bit 4 Bit 3
5439
Data 1 Data 2
[3] [3]
A
Master tansmit mode Master receive mode
A
16.4.5 Slave Receive
Operation
Figure 16.22 Example
of Slave Receive Mode
Operation Timing (1)
(MLS = ACKB = 0
,
HNDS = 0)
464 Figure title amended
Figure 16.23 Example
of Slave Receive Mode
Operation Timing (2)
(MLS = ACKB = 0
,
HNDS = 0)
464 Figure title amended
16.6 Usage Notes 483 10. Notes on WAIT Function
Description added
Figure 16.35 ICDR
Read and ICCR
Access Riming in
Slave Transmit Mode
485 Figure 16.35 amended
R/
W
487,
488
14. Notes on Arbitration Lost in Master Mode
Description added