Datasheet

Section 5 Interrupt Controller

Rev. 3.00 Mar 21, 2006 page 101 of 788

REJ09B0300-0300

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n = 7 to 0

Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0

When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0.

When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and

WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the

IRQ7 pin will be ignored.

Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied,

regardless of the IER setting, refer to a needed flag only.

KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7

to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE7 to WUE0. When

pins KIN15 to KIN0 and WUE7 to WUE0 are used for key-sense input or wakeup event, clear the

corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and

wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input

should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8

generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin

conditions for interrupt request generation, enable of interrupt requests, settings of interrupt

control levels, and status display of interrupt requests depend on each setting and display of the

IRQ7 or IRQ6 interrupt.

When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt

input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing

must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6

or IRQ7).