Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 21, 2006 page 91 of 788
REJ09B0300-0300
5.2 Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Symbol I/O Function
NMI Input Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ7 to IRQ0 Input Maskable external interrupts
Rising edge, falling edge, or both edges, or level sensing, can
be selected individually for each pin.
KIN15 to KIN0 Input Maskable external interrupts
Falling edge or level sensing can be selected.
WUE7 to WUE0
*
Input Maskable external interrupts
Falling edge or level sensing can be selected.
Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version).
5.3 Register Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
• Interrupt control registers A to C (ICRA to ICRC)
• Address break control register (ABRKCR)
• Break address registers A to C (BARA to BARC)
• IRQ sense control registers (ISCRH, ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)
• Wake-up event interrupt mask register (WUEMRB)