Datasheet

Section 4 Exception Handling

Rev. 3.00 Mar 21, 2006 page 84 of 788

REJ09B0300-0300

RES

Internal address bus

Internal read signal

Internal write signal

Internal data bus

Vector

fetch

(1) Reset exception handling vector address ((1) = H'0000)

(2) Start address (contents of reset exception handling vector address)

(3) Start address ((3) = (2))

(4) First program instruction

(1) (3)

High

Internal

processing

Prefetch of first program

instruction

(2) (4)

Figure 4.1 Reset Sequence (Mode 3)

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled

After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all

modules except the DTC operate in module stop mode. Therefore, the registers of on-chip

peripheral modules cannot be read from or written to. To read from and write to these registers,

clear module stop mode.