Datasheet

Rev. 3.00 Mar 21, 2006 page xii of liv
Item Page Revision (See Manual for Details)
14.4.2 Interval Timer
Mode
Figure 14.4 OVF Flag
Set Timing
354 Figure 14.4 amended
φ
TCNT
H'FF H'00
Overflow signal
(internal signal)
OVF
14.6.2 Conflict
between Timer
Counter (TCNT) Write
and Increment
Figure 14.7 Conflict
between TCNT Write
and Increment
357 Figure 14.7 amended
Address
φ
Internal write signal
T
1
T
2
TCNT write cycle
15.1 Features
Figure 15.1 Block
Diagram of SCI
360 Figure legend amended
(Before) SCMR:
Smart card mode register → (After) SCMR:
Serial interface mode register
16.3.5 I
2
C Bus
Control Register
(ICCR)
424 Table amended
Bit Bit Name Initial Value R/W Description
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
2
C bus
format. In slave receive mode with I
2
C bus format, the
R/
W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit mode
automatically by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.