Datasheet

Rev. 3.00 Mar 21, 2006 page x of liv
Item Page Revision (See Manual for Details)
5.6 Interrupt Control
Modes and Interrupt
Operation
Table 5.4 Interrupt
Control Modes
105 Table amended
Description
Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
3-level interrupt mask control is
performed by the
I and UI bits. Priority
levels can be set with ICR.
5.6.5 DTC Activation
by Interrupt
114 Description amended
… the DTCE bit of DTC's
DTCER, and the DISEL bit of …
7.2.8 DTC Vector
Register (DTVECR)
151 Description amended
… software activation interrupt.
DTVECR is initialized to H'00 at a reset and in hardware
standby mode.
7.4 Location of
Register Information
and DTC Vector Table
Table 7.1 Interrupt
Sources, DTC Vector
Addresses, and
Corresponding DTCEs
154 Note 2 amended
Note: 2. Not supported by the H8S/2148B
and H8S/2145B (5-V
version).
8.1 Overview 167 Description amended
… in addition to DD
R, to control the on/off …
Table 8.1 Port
Functions of
H8S/2140B,
H8S/2141B,
H8S/2145B, and
H8S/2148B
171 Note * amended
Note: * Not supported by the H8S/2148B
and H8S/2145B (5-V
version).
8.4.4 Pin Functions 181 • P37/D15/HDB7/SERIRQ
*
, ... , P30/D8/HDB0/LAD0
*
Note amended
Note: * Not supported by the H8S/2148B
and H8S/2145B (5-V
version).