Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 751 of 788
REJ09B0300-0300
Timing of On-Chip Peripheral Modules: Tables 27.23 to 27.26 show the on-chip peripheral
module timing. The only on-chip peripheral modules that can operate in subclock operation (φ =
32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog
timer, and the 8-bit timer (channels 0 and 1).
Table 27.23 Timing of On-Chip Peripheral Modules (1)
Condition A: V
CC
= 5.0 V ±10%, V
CC
B = 5.0 V ±10%, V
SS
= 0 V,
φ = 32.768 kHz
*
, 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition B: V
CC
= 4.0 V to 5.5 V, V
CC
B = 4.0 V to 5.5 V, V
SS
= 0 V,
φ = 32.768 kHz
*
, 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition C: V
CC
= 2.7 V to 3.6 V, V
CC
B = 2.7 V to 5.5 V, V
SS
= 0 V, φ = 32.768 kHz
*
,
2 MHz to maximum operating frequency, T
a
= –20 to +75°C
Condition
A
Condition
B
Condition
C
10 MHz 16 MHz 20 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
Output data delay time t
PWD
— 100 — 50 — 50
Input data setup time t
PRS
50 — 30 — 30 —
I/O ports
Input data hold time t
PRH
50 — 30 — 30 —
ns Figure 27.16
FRT Timer output delay time t
FTOD
— 100 — 50 — 50
Timer input setup time t
FTIS
50 — 30 — 30 —
Figure 27.17
Timer clock input setup
time
t
FTCS
50
— 30 — 30 —
ns
Single edge t
FTCWH
1.5 — 1.5 — 1.5 —Timer clock
pulse width
Both edges t
FTCWL
2.5 — 2.5 — 2.5 —
t
cyc
Figure 27.18
TMR Timer output delay time t
TMOD
— 100 — 50 — 50 Figure 27.19
Timer reset input setup
time
t
TMRS
50 — 30 — 30 — Figure 27.21
Timer clock input setup
time
t
TMCS
50 — 30 — 30 —
ns
Figure 27.20