Datasheet

Section 25 Power-Down Modes
Rev. 3.00 Mar 21, 2006 page 645 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB) input
from the EXCL pin is sampled using the clock (φ) generated
by the system clock pulse generator. Clear this bit to 0
when φ is 5 MHz or more.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3 

 0R/WReserved
An undefined value is read from this bit. This bit should not
be set to 1.
2 to 0 

 All 0 R Reserved
These bits are always read as 0 and cannot be modified.
25.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in
module units. Each module can enter module stop mode by setting the corresponding bit to 1.
• MSTPCRH
Bit Bit Name Initial Value R/W Corresponding Module
7 MSTP15 0
*
R/W
6 MSTP14 0 R/W Data transfer controller (DTC)
5 MSTP13 1 R/W 16-bit free-running timer (FRT)
4 MSTP12 1 R/W 8-bit timers (TMR_0, TMR_1)
3 MSTP11 1 R/W 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)
2 MSTP10 1 R/W D/A converter
1 MSTP9 1 R/W A/D converter
0 MSTP8 1 R/W 8-bit timers (TMR_X, TMR_Y), timer connection
Note: * Do not set this bit to 1.