Datasheet

Section 25 Power-Down Modes
Rev. 3.00 Mar 21, 2006 page 642 of 788
REJ09B0300-0300
25.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode, subactive mode, or
watch mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode
1: Shifts to watch mode or high-speed mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
Selects the wait time for clock stabilization from clock
oscillation start when canceling software standby mode,
watch mode, or subactive mode. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on the
operating frequency. Table 25.1 shows the relationship
between the STS2 to STS0 values and wait time.
With an external clock, there are no specific wait
requirements. Normally the minimum value is
recommended.
3  0RReserved
This bit is always read as 0, and cannot be modified.