Datasheet

Section 24 Clock Pulse Generator
Rev. 3.00 Mar 21, 2006 page 637 of 788
REJ09B0300-0300
Table 24.4 External Clock Output Stabilization Delay Time
Conditions: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
SS
= AV
SS
= 0 V
Item Symbol Min. Max. Unit Remarks
External clock output stabilization
delay time
t
DEXT
* 500 — µs Figure 24.6
Note: * t
DEXT
includes a RES pulse width (t
RESW
).
t DEXT *
RES
(Internal and external)
EXTAL
STBY
V
CC
2.7 V
V
IH
φ
Note: * The external clock output stabilization delay time (t
DEXT ) includes a RES pulse width (t RESW ).
Figure 24.6 Timing of External Clock Output Stabilization Delay Time
24.2 Duty Correction Circuit
The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects
the duty of a clock that is output from the oscillator, and generates the system clock (φ).
24.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.