Datasheet

Section 24 Clock Pulse Generator
Rev. 3.00 Mar 21, 2006 page 636 of 788
REJ09B0300-0300
Table 24.3 External Clock Input Conditions
V
CC
= 2.7 to 3.6 V V
CC
= 5.0 V ±
±±
± 10 %
%%
%
Item Symbol Min Max Min Max Unit Test Conditions
External clock
input pulse width
low level
t
EXL
40 — 20 — ns
External clock
input pulse width
high level
t
EXH
40 — 20 — ns
External clock
rising time
t
EXr
—10 —5 ns
External clock
falling time
t
EXf
—10 —5 ns
Figure 24.5
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHzClock pulse width
low level
t
CL
80 — 80 — ns φ < 5 MHz
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHzClock pulse width
high level
t
CH
80 — 80 — ns φ < 5 MHz
Figure
28.6
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 24.5 External Clock Input Timing
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t
DEXT
) has passed. As the clock signal output is not determined during the t
DEXT
cycle, a reset
signal should be set to low to hold it in reset state. Table 24.4 shows the external clock output
stabilization delay time. Figure 24.6 shows the timing of the external clock output stabilization
delay time.