Datasheet

Section 23 ROM
Rev. 3.00 Mar 21, 2006 page 611 of 788
REJ09B0300-0300
23.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 23.2.
Table 23.2 Pin Configuration
Pin Name I/O Function
RES Input Reset
MD1 Input Sets this LSI’s operating mode
MD0 Input Sets this LSI’s operating mode
P92 Input Sets this LSI’s operating mode
P91 Input Sets this LSI’s operating mode
P90 Input Sets this LSI’s operating mode
TxD1 Output Serial transmit data output
RxD1 Input Serial receive data input
23.5 Register Descriptions
The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2,
the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the
serial/timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
23.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode,
program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to
section 23.8, Flash Memory Programming/Erasing.
FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode,
sub-active mode, sub-sleep mode, or watch mode.