Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 517 of 788
REJ09B0300-0300
18.3.3 Input Data Register (IDR)
IDR is a register in which data to be input from the host processor to the slave processor (this LSI)
is stored.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7
6
5
4
3
2
1
0
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0








R
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
When CSn (n = 1 to 4) is low, information on the
host data bus is written into IDR_n at the rising
edge of IOW. The HA0 state is also latched into
the C/D bit in STR_n to indicate whether the
written information is a command or data.
18.3.4 Output Data Register 1 (ODR)
ODR is a register in which data to be output from the slave processor (this LSI) to the host
processor is stored.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7
6
5
4
3
2
1
0
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0








R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
The ODR_n contents are output on the host data
bus when HA0 is low, CSn (n = 1 to 4) is low,
and IOR is low.