Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 512 of 788
REJ09B0300-0300
18.3 Register Descriptions
XBS has the following registers. XBS registers HICR, IDR_1, IDR_2, ODR_1, ODR_2, STR_1,
and STR_2 can only be accessed when the HIE bit is set to 1 in SYSCR. For details on SYSCR,
refer to section 3.2.2, System Control Register (SYSCR).
• System control register 2 (SYSCR2)
• Host interface control register (HICR)
• Host interface control register 2 (HICR2)
• Input data register (IDR)
• Output data register (ODR)
• Status register (STR)
18.3.1 System Control Register 2 (SYSCR2)
SYSCR2 controls the operations of port 6 and host interface.
Bit Bit Name Initial Value R/W Description
7
6
KWUL1
KWUL0
0
0
R/W
R/W
Key Wakeup Level 1 and 0
Sets the port 6 input level. The input level of port-6
multiplexing pins is also changed by these settings.
00: Port 6 is in the standard input level
01: Port 6 is in input level 1
10: Port 6 is in input level 2
11: Port 6 is in input level 3
5 P6PUE 0 R/W Port 6 Input Pull-Up MOS Extra (P6PUE)
Controls and selects the current specification for the
port 6 input pull-up MOS.
0: Standard current specification
1: Current limited specification
4  0  Reserved
Only 0 should be written to this bit.