Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 511 of 788
REJ09B0300-0300
18.2 Input/Output Pins
Table 18.1 lists the input and output pins of the XBS module.
Table 18.1 Pin Configuration
Name Abbreviation Port I/O Function
I/O read IOR P93 Input Host interface read signal
I/O write IOW P94 Input Host interface write signal
Chip select 1 CS1 P95 Input Host interface chip select signal for IDR_1,
ODR_1, STR_1
CS2 P81Chip select 2
*
ECS2 P90
Input Host interface chip select signal for IDR_2,
ODR_2, STR_2
Chip select 3 CS3 PB2 Input Host interface chip select signal for IDR_3,
ODR_3, STR_3
Chip select 4 CS4 PB3 Input Host interface chip select signal for IDR_4,
ODR_4, STR_4
Command/data HA0 P80 Input Host interface address select signal
In host read access, this signal selects the
status registers (STR_1 to STR_4) or data
registers (ODR_1 to ODR_4). In host write
access to the data registers (IDR_1 to
IDR_4), this signal indicates whether the
host is writing a command or data.
Data bus HDB7 to HDB0 P37 to
P30
I/O Host interface data bus
Host interrupt 11 HIRQ11 P43 Output Interrupt output 11 to host
Host interrupt 1 HIRQ1 P44 Output Interrupt output 1 to host
Host interrupt 12 HIRQ12 P45 Output Interrupt output 12 to host
Host interrupt 3 HIRQ3 PB0 Output Interrupt output 3 to host
Host interrupt 4 HIRQ4 PB1 Output Interrupt output 4 to host
Gate A20 GA20 P81 Output A20 gate control signal output
HIF shutdown HIFSD P82 Input Host interface shutdown control signal
Note: * Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in
HICR. XBS channel 2 and the CS2 pin can be used when CS2E = 1. When CS2E = 1,
CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this manual,
both are referred to as CS2.