Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 510 of 788
REJ09B0300-0300
Figure 18.1 shows a block diagram of the XBS.
Internal interrupt signals
IBF2
IBF1
Control logic
HDB7 to HDB0
IDR_3
ODR_3
STR_3
IDR_4
ODR_4
STR_4
HICR2
Module data bus
Host data bus
Host
interrupt
request
Fast
A20 gate
control
Port 4, port 8, port B
Internal data bus
Bus
interface
CS1
C
S2/ECS2
CS3
CS4
IOR
IOW
HA0
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
IDR_1
ODR_1
STR_1
IDR_2
ODR_2
STR_2
HICR
IBF4
IBF3
Legend:
IDR_1:
IDR_2:
ODR_1:
ODR_2:
STR_1:
STR_2:
HICR:
Input data register_1
Input data register_2
Output data register_1
Output data register_2
Status register_1
Status register_2
Host interface control register
IDR_3:
IDR_4:
ODR_3:
ODR_4:
STR_3:
STR_4:
HICR2:
Input data register_3
Input data register_4
Output data register_3
Output data register_4
Status register_3
Status register_4
Host interface control register 2
Figure 18.1 Block Diagram of XBS