Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 484 of 788
REJ09B0300-0300
11. Note on IRIC flag clear when the wait function is used
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I
2
C bust interface
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
SCL
IRIC
[1] SCL = low determination
VIH
[2] IRIC clear
SDA
Secures a high period
SCL = low detected
Figure 16.34 IRIC Flag Clearing Timing When WAIT = 1
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.