Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 460 of 788
REJ09B0300-0300
SDA
(master output)
SDA
(slave output)
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Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
Address +R/W
Address +R/W
Undefined value
[8] IRIC clear [10] ICDR read (dummy read)
User processing
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SCL
(Pin waveform)
Start condition generation
Slave address
Data 1
[6]
A
R/W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 16.19 Example of Slave Receive Mode Operation Timing (1)
(MLS = 0, HNDS= 1)