Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 448 of 788
REJ09B0300-0300
SDA
(master output)
SDA
(slave output)
21436587989
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRE
IRTR
ICDR
SCL
(master output)
Start condition issuance
Data 2
[9] ICDR write
[9] IRIC clear
[12] IRIC clear
[11] ACKB read [12] Set BBSY=1and
SCP=0
(Stop condition issuance)
IRIC
A
[10]
[7]
Data 1
Data 1 Data 2
User processing
Figure 16.10 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)
16.4.4 Master Receive Operation
In I
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.