Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 430 of 788
REJ09B0300-0300
Table 16.5 Flags and Transfer States (Slave Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
00000000000—0 Idle state (flag clearing
required)
001↑ 0000↓ 0000—1↑ Start condition detected
01↑/0
*
1
10000—1↑ 001↑ 1 SAR match in first frame
(SARX ≠ SAR)
0010000—1↑ 1↑ 01↑ 1 General call address
match in first frame
(SARX ≠ H'00)
01↑/0
*
1
1001↑ 1↑ —0001↑ 1 SARS match in first
frame (SAR ≠ SARX)
01100————0 1↑ — — Transmission end (ACKE
= 1 and ACKB =1 )
011001↑/0
*
2
———0 0 —1↑ Transmission end with
ICDRE = 0
01100——0↓ 0↓ 00—0↓ ICDR write with the
above state
01100————0 0 —1 Transmission end with
ICDRE = 1
01100——0↓ 0↓ 00—0↓ ICDR write with the
above state
011001↑/0
*
2
—0000—1↑ Automatic data transfer
from ICDRT to ICDRS
with the above state
001001↑/0
*
2
—————1↑ — Reception end with
ICDRF=0
00100——0↓ 0↓ 0↓ —0↓ — ICDR read with the above
state
00100——————1 — Reception end with
ICDRF = 1
00100——0↓ 0↓ 0↓ —0↓ — ICDR read with the above
state
001001↑/0
*
2
—000—1↑ — Automatic data transfer
from ICDRS to ICDRR
with the above state
0—0↓ 1↑/0
*
3
0/1↑
*
3
———————0↓ Stop condition detected
Legend:
0: 0-state retained
1: 1-state retained
—: Previous state retained
0↓: Cleared to 0
1↑: Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.