Datasheet

Rev. 3.00 Mar 21, 2006 page xlvi of liv
Figure 24.5 External Clock Input Timing ............................................................................... 636
Figure 24.6 Timing of External Clock Output Stabilization Delay Time ............................... 637
Figure 24.7 Subclock Input Timing ........................................................................................ 638
Figure 24.8 Processing for X1 and X2 Pins ............................................................................ 640
Figure 24.9 Note on Board Design of Oscillator Circuit Section............................................ 640
Section 25 Power-Down Modes
Figure 25.1 Mode Transition Diagram.................................................................................... 647
Figure 25.2 Medium-Speed Mode Timing.............................................................................. 650
Figure 25.3 Application Example in Software Standby Mode................................................ 652
Figure 25.4 Hardware Standby Mode Timing......................................................................... 653
Section 27 Electrical Characteristics
Figure 27.1 Darlington Pair Drive Circuit (Example)............................................................. 708
Figure 27.2 LED Drive Circuit (Example).............................................................................. 709
Figure 27.3 Output Load Circuit............................................................................................. 710
Figure 27.4 Connection of VCL Capacitor ............................................................................. 724
Figure 27.5 Connection of VCL Capacitor ............................................................................. 761
Figure 27.6 System Clock Timing .......................................................................................... 762
Figure 27.7 Oscillation Settling Timing.................................................................................. 762
Figure 27.8 Oscillation Setting Timing (Exiting Software Standby Mode)............................ 763
Figure 27.9 Reset Input Timing .............................................................................................. 764
Figure 27.10 Interrupt Input Timing ......................................................................................... 764
Figure 27.11 Basic Bus Timing (Two-State Access) ................................................................ 765
Figure 27.12 Basic Bus Timing (Three-State Access) .............................................................. 766
Figure 27.13 Basic Bus Timing (Three-State Access with One Wait State)............................. 767
Figure 27.14 Burst ROM Access Timing (Two-State Access) ................................................. 768
Figure 27.15 Burst ROM Access Timing (One-State Access).................................................. 769
Figure 27.16 I/O Port Input/Output Timing .............................................................................. 770
Figure 27.17 FRT Input/Output Timing.................................................................................... 770
Figure 27.18 FRT Clock Input Timing ..................................................................................... 771
Figure 27.19 8-Bit Timer Output Timing.................................................................................. 771
Figure 27.20 8-Bit Timer Clock Input Timing.......................................................................... 771
Figure 27.21 8-Bit Timer Reset Input Timing........................................................................... 771
Figure 27.22 PWM, PWMX Output Timing............................................................................. 772
Figure 27.23 SCK Clock Input Timing..................................................................................... 772
Figure 27.24 SCI Input/Output Timing (Synchronous Mode) .................................................. 772
Figure 27.25 A/D Converter External Trigger Input Timing .................................................... 772
Figure 27.26 WDT Output Timing (RESO).............................................................................. 773
Figure 27.27 Host Interface (XBS) Timing............................................................................... 773
Figure 27.28 Keyboard Buffer Controller Timing .................................................................... 774